 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| d a t a sh eet preliminary speci?cation file under integrated circuits, ic01 1999 may 10 integrated circuits UDA1325 universal serial bus (usb) codec
1999 may 10 2 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 features general high quality usb-compliant audio/hid device supports 12 mbits/s serial data transmission fully usb plug and play operation supports bus-powered and self-powered operation 3.3 v power supply low power consumption with optional efficient power control on-chip clock oscillator, only an external crystal is required. audio playback channel one isochronous output endpoint supports multiple audio data formats (8, 16 and 24 bits) adaptive sample frequency support from 5 to 55 khz one master 20-bit i 2 s digital stereo playback output, i 2 s and lsb justified serial formats one slave 20-bit i 2 s digital stereo playback input, i 2 s and lsb justified serial formats selectable volume control for left and right channel soft mute control digital bass and treble tone control selectable on-chip digital de-emphasis low total harmonic distortion (typical 90 db) high signal-to-noise ratio (typical 95 db) one stereo line output. audio recording channel one isochronous input endpoint supports multiple audio data formats (8, 16 and 24 bits) twelve selectable sample rates (4, 8, 16 or 32 khz; 5.5125, 11.025, 22.05 or 44.1 khz; 6, 12, 24 or 48 khz) via analog pll (apll). selectable sample rate between 5 to 55 khz via a second oscillator (optional) one slave 20-bit i 2 s digital stereo recording input, i 2 s and lsb justified serial formats programmable gain amplifier for left and right channel low total harmonic distortion (typical 85 db) high signal-to-noise ratio (typical 90 db) one stereo line/microphone input. usb endpoints 2 control endpoints 2 interrupt endpoints 1 isochronous data sink endpoint 1 isochronous data source endpoint. document references usb specification usb device class definition for audio devices device class definition for human interface devices (hid) usb hid usage table . usb common class specification . 1999 may 10 3 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 applications usb monitors usb speakers usb microphones usb headsets usb telephone/answering machines usb links in consumer audio devices. general description the UDA1325 is a single chip stereo usb codec incorporating bitstream converters designed for implementation in usb-compliant audio peripherals and multimedia audio applications. it contains a usb interface, an embedded microcontroller, an analog-to-digital interface (adif) and an asynchronous digital-to-analog converter (adac). the usb interface consists of an analog front-end and a usb processor. the analog front-end transforms the differential usb data into a digital data stream. the usb processor buffers the incoming and outgoing data from the analog front-end and handles all low-level usb protocols. the usb processor selects the relevant data from the universal serial bus, performs an extensive error detection and separates control information and audio information. the control information is made accessible to the microcontroller. at playback, the audio information becomes available at the digital i 2 s output of the digital i/o module or is fed directly to the adac. at recording, the audio information is delivered by the adif or by the digital i 2 s input of the i 2 s-bus interface. all i 2 s inputs and i 2 s outputs support standard i 2 s-bus format and the lsb justified serial data format with word lengths of 16, 18 and 20 bits. via the digital i/o module with its i 2 s input and output, an external dsp can be used for adding extra sound processing features for the audio playback channel. the microcontroller is responsible for handling the high-level usb protocols, translating the incoming control requests and managing the user interface via general purpose pins and an i 2 c-bus. the adac enables the wide and continuous range of playback sampling frequencies. by means of a sample frequency generator (sfg), the adac is able to reconstruct the average sample frequency from the incoming audio samples. the adac also performs the playback sound processing. the adac consists of a fifo, an unique audio feature processing dsp, the sfg, digital filters, a variable hold register, a noise shaper (ns) and a filter stream dac (fsdac) with line output drivers. the audio information is applied to the adac via the usb processor or via the digital i 2 s input of the digital i/o module. the adif consists of an programmable gain amplifier (pga), an analog-to-digital converter (adc) and a decimator filter (df). an analog phase lock loop (apll) or oscillator is used for creating the clock signal of the adif. the clock frequency for the adif can be controlled via the microcontroller. several clock frequencies are possible for sampling the analog input signal at different sampling rates. the wide dynamic range of the bitstream conversion technique used in the UDA1325 for both the playback and recording channel guarantees a high audio sound quality. ordering information type number package name description version UDA1325ps sdip42 plastic shrink dual in-line package; 42 leads (600 mil) sot270-1 UDA1325h qfp64 plastic quad ?at package; 64 leads (lead length 1.95 mm); body 14 20 2.8 mm sot319-2 1999 may 10 4 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 quick reference data note 1. exclusive the idde current which depends on the components connected to the i/o pins. symbol parameter conditions min. typ. max. unit supplies v dde supply voltage periphery 4.75 5.0 5.25 v v ddi supply voltage core 3.0 3.3 3.6 v i dd(tot) total supply current - 60 tbf ma i dd(tot)(ps) total supply current in power-saving mode note 1 - 360 -m a dynamic performance dac (thd + n)/s total harmonic distortion plus noise-to-signal ratio f s = 44.1 khz; r l =5k w f i = 1 khz (0 db) -- 90 - 80 db - 0.0032 0.01 % f i = 1 khz ( - 60 db) -- 30 - 20 db - 3.2 10 % s/n signal-to-noise ratio at bipolar zero a-weighted at code 0000h 90 95 - dba v o(fs)(rms) full-scale output voltage (rms value) v dd = 3.3 v - 0.66 - v dynamic performance pga and adc (thd + n)/s total harmonic distortion plus noise-to-signal ratio f s = 44.1 khz; pga gain = 0 db f i = 1 khz; (0 db); v i = 1.0 v (rms) -- 85 - 80 db - 0.0056 0.01 % f i = 1 khz ( - 60 db) -- 30 - 20 db - 3.2 10.0 % s/n signal-to-noise ratio v i = 0.0 v 90 95 - dba general characteristics f i(s) audio input sample frequency 5 - 55 khz t amb operating ambient temperature 0 25 70 c 1999 may 10 5 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 block diagram fig.1 block diagram (qfp64 package). handbook, full pagewidth mgm108 timing analog pll osc 48 mhz osc adc 24 (19) 27 25 (20) 26 (21) 28 (22) 52 (39) 53 (40) 54 (41) 55 (42) 63 (4) 1 (5) 2 (6) 13 (14) 17 (16) 15 (15) (12) 11 (13) 12 (10) 9 (11) 10 (23) 32 (24) 33 (29) 38 (30) 39 (33) 42 (35) 44 analog front-end usb-processor digital i/o fifo audio feature processing dsp upsample filters variable hold register 3rd-order noise shaper reference voltage 57 (1) 59 (2) 61 (3) 43 (34) 47 (36) 8 (9) 6 (8) micro- controller test control block sample frequency generator mux i 2 s-bus interface decimator filter pga left sd adc pga right sd adc left dac right dac 49 (37) 51 (38) 45, 46 41 (32) 40 (31) v ref(ad) v ref(da) (28) 37 (25) 34 (27) 36 (26) 35 (7) 4 (18) 21 (17) 19 n.c. UDA1325 + - - + vrn vinr v ssa2 vinl v ssa1 v dda1 voutr rtcb gp4/bcko shtcb d - 7, 5, 3, 64, 62, 60, 58, 56 p0.7 to p0.0 14, 16, 18, 20, 22, 23, 29, 30 p2.0 to p2.7 d + v ddi v ssi v dde gp1/di gp0/bcki v dda2 bck 48 ea 50 ale ws da 31 psen v ssa3 xtal2a v dda3 vrp gp2/do gp3/wso xtal1a sda v ssx xtal1b xtal2b clk v ddx v sso voutl tc scl v ddo v sse gp5/wsi the pin numbers given in parenthesis refer to the sdip42 version. 1999 may 10 6 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 pinning symbol pin qfp64 pin sdip42 i/o description gp3/wso 1 5 i/o general purpose pin 3 or word select output gp4/bcko 2 6 i/o general purpose pin 4 or bit clock output p0.5 3 - i/o port 0.5 of the microcontroller shtcb 4 7 i shift clock of the test control block (active high) p0.6 5 - i/o port 0.6 of the microcontroller d - 6 8 i/o negative data line of the differential data bus, conforms to the usb standard p0.7 7 - i/o port 0.7 of the microcontroller d+ 8 9 i/o positive data line of the differential data bus, conforms to the usb standard v ddi 910 - digital supply voltage for core v ssi 10 11 - digital ground for core v sse 11 12 - digital ground for i/o pads v dde 12 13 - digital supply voltage for i/o pads gp1/di 13 14 i/o general purpose pin 1 or data input p2.0 14 - i/o port 2.0 of the microcontroller gp5/wsi 15 15 i/o general purpose pin 5 or word select input p2.1 16 - i/o port 2.1 of the microcontroller gp0/bcki 17 16 i/o general purpose pin 0 or bit clock input p2.2 18 - i/o port 2.2 of the microcontroller scl 19 17 i/o serial clock line i 2 c-bus p2.3 20 - i/o port 2.3 of the microcontroller sda 21 18 i/o serial data line i 2 c-bus p2.4 22 - i/o port 2.4 of the microcontroller p2.5 23 - i/o port 2.5 of the microcontroller v ssx 24 19 - crystal oscillator ground (48 mhz) xtal1b 25 20 i crystal input (analog; 48 mhz) xtal2b 26 21 o crystal output (analog; 48 mhz) clk 27 - o 48 mhz clock output signal v ddx 28 22 - supply crystal oscillator (48 mhz) p2.6 29 - i/o port 2.6 of the microcontroller p2.7 30 - i/o port 2.7 of the microcontroller psen 31 - i/o program store enable (active low) v ddo 32 23 - supply voltage for operational ampli?er v sso 33 24 - operational ampli?er ground voutl 34 25 o voltage output left channel tc 35 26 i test control input (active high) rtcb 36 27 i asynchronous reset input of the test control block (active high) voutr 37 28 o voltage output right channel 1999 may 10 7 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 v dda1 38 29 - analog supply voltage 1 v ssa1 39 30 - analog ground 1 v ref(da) 40 31 o reference voltage output dac v ref(ad) 41 32 o reference voltage output adc v dda2 42 33 - analog supply voltage 2 vinl 43 34 i input signal left channel pga v ssa2 44 35 - analog ground 2 n.c. 45 -- not connected n.c. 46 -- not connected vinr 47 36 i input signal right channel pga ea 48 -- external access (active low) vrn 49 37 i negative reference input voltage adc ale 50 -- address latch enable (active high) vrp 51 38 i positive reference input voltage adc v dda3 52 39 - supply voltage for crystal oscillator and analog pll xtal2a 53 40 o crystal output (analog; adc) xtal1a 54 41 i crystal input (analog; adc) v ssa3 55 42 - crystal oscillator and analog pll ground p0.0 56 - i/o port 0.0 of the microcontroller da 57 1 i data input (digital) p0.1 58 - i/o port 0.1 of the microcontroller ws 59 2 i word select input (digital) p0.2 60 - i/o port 0.2 of the microcontroller bck 61 3 i bit clock input (digital) p0.3 62 - i/o port 0.3 of the microcontroller gp2/do 63 4 i/o general purpose pin 2 or data output p0.4 64 - i/o port 0.4 of the microcontroller symbol pin qfp64 pin sdip42 i/o description 1999 may 10 8 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 fig.2 pin configuration (qfp64 package). handbook, full pagewidth UDA1325h mgl349 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 gp3/wso gp4/bcko p0.5 shtcb p0.6 d - p0.7 d + v ddi v ssi v sse v dde gp1/di p2.0 gp5/wsi p2.1 gp0/bcki p2.2 scl vrp ale vrn ea vinr n.c. n.c. v ssa2 vinl v dda2 v ref(ad) v ref(da) v ssa1 v dda1 voutr rtcb tc voutl v sso 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 p0.4 gp2/do p0.3 bck p0.2 ws p0.1 da p0.0 v ssa3 xtal1a xtal2a v dda3 p2.3 sda p2.4 p2.5 v ssx xtal1b xtal2b clk v ddx p2.6 p2.7 psen v ddo 1999 may 10 9 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 fig.3 pin configuration (sdip42 package). handbook, halfpage UDA1325 mgm106 1 2 42 41 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 v ssa3 xtal1a xtal2a v dda3 vrp vrn vinr v ssa2 vinl v dda2 v ref(ad) v ref(da) v ssa1 v dda1 voutr rtcb tc voutl v sso v ddo v ddx da ws bck gp2/do gp3/wso gp4/bcko shtcb d - d + v ddi v ssi v sse v dde gp1/di gp5/wsi gp0/bcki scl sda v ssx xtal1b xtal2b functional description the universal serial bus (usb) data and power is transferred via the usb over a 4-wire cable. the signalling occurs over two wires and point-to-point segments. the signals on each segment are differentially driven into a cable of 90 w intrinsic impedance. the differential receiver features input sensitivity of at least 200 mv and sufficient common mode rejection. the analog front-end the analog front-end is an on-chip generic usb transceiver. it is designed to allow voltage levels up to v dd from standard or programmable logic to interface with the physical layer of the usb. it is capable of receiving and transmitting serial data at full speed (12 mbits/s). the usb processor the usb processor forms the interface between the analog front-end, the adif, the adac and the microcontroller. the usb processor consists of: a bit clock recovery circuit the philips serial interface engine (psie) the memory management unit (mmu) the audio sample redistribution (asr) module. bit clock recovery the bit clock recovery circuit recovers the clock from the incoming usb data stream using four times over-sampling principle. it is able to track jitter and frequency drift specified by the usb specification. philips serial interface engine (psie) the philips sie implements the full usb protocol layer. it translates the electrical usb signals into data bytes and control signals. depending upon the usb device address and the usb endpoint address, the usb data is directed to the correct endpoint buffer. the data transfer could be of bulk, isochronous, control or interrupt type. the functions of the psie include: synchronization pattern recognition, parallel/serial conversion, bit stuffing/de-stuffing, crc checking/generation, pid verification/generation, address recognition and handshake evaluation/generation. the amount of bytes/packet on all endpoints is limited by the psie hardware to 8 bytes/packet, except for both isochronous endpoints (336 bytes/packet). 1999 may 10 10 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 memory management unit (mmu) and integrated ram the mmu and integrated ram handle the temporary data storage of all usb packets that are received or sent over the bus. the mmu and integrated ram handle the differences between data rate of the usb and the application allowing the microcontroller to read and write usb packets at its own speed. the audio data is transferred via an isochronous data sink endpoint or source endpoint and is stored directly into the ram. consequently, no handshaking mechanism is used. audio sample redistribution (asr) the asr reads the audio samples from the mmu and integrated ram and distributes these samples equidistant over a 1 ms frame period. the distributed audio samples are translated by the digital i/o module to standard i 2 s-bus format or 16, 18 or 20 bits lsb-justified i 2 s-bus format. the asr generates the bit clock output (bcko) and the word select output signal (wso) of the i 2 s output. the 80c51 microcontroller the microcontroller receives the control information selected from the usb by the usb processor. it can be used for handling the high-level usb protocols and the user interfaces. the microcontroller does not handle the audio stream. the major task of the software process that is mapped upon the microcontroller, is to control the different modules of the UDA1325 in such a way that it behaves as a usb device. the embedded 80c51 microcontroller is compatible with the 80c51 family of microcontrollers described in the 80c51 family single-chip 8-bit microcontrollers of data handbook ic20, which should be read in conjunction with this data sheet. the internal rom size is 12 kbyte. the internal ram size is 256 byte. a watchdog timer is not integrated. the analog-to-digital interface (adif) the adif is used for sampling an analog input signal from a microphone or line input and sending the audio samples to the usb interface. the adif consists of a stereo programmable gain amplifier (pga), a stereo analog-to-digital converter (adc) and decimation filters (dfs). the sample frequency of the adc is determined by the adc clock (see section the clock source of the analog-to-digital interface). the user can also select a digital serial input instead of an analog input. in this event the sample frequency is determined by the continuous ws clock with a range between 5 to 55 khz. digital serial input is possible with four formats (i 2 s-bus, 16, 18 or 20 bits lsb-justified). programmable gain ampli?er circuit (pga) this circuit can be used for a microphone or line input. the input audio signals can be amplified by seven different gains ( - 3 db, 0 db, 3 db, 9 db, 15 db, 21 db and 27 db). the gain settings are given in table 17. the analog-to-digital converter (adc) the stereo adc of the UDA1325 consists of two 3rd-order sigma-delta modulators. they have a modified ritchie-coder architecture in a differential switched capacitor implementation. the oversampling ratio is 128. both adcs can be switched off in power saving mode (left and right separate). the adc clock is generated by the analog pll or the adc oscillator. the decimation filter (df) the decimator filter converts the audio data from 128f s down to 1f s with a word width of 8, 16 or 24 bits. this data can be transmitted over the usb as mono or stereo in 1, 2 or 3 bytes/sample. the decimator filters are clocked by the adc clock. 1999 may 10 11 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 the clock source of the analog-to-digital interface the clock source of the adif is the analog pll or the adc oscillator. the preferred clock source can be selected. the adc clock used for the adc and decimation filters is obtained by dividing the clock signal coming from the analog pll or from the adc oscillator by a factor q. using the analog pll the user can select 3 basic apll clock frequencies (see table 1). by connecting the appropriate crystal the user can choose any clock signal between 8.192 and 14.08 mhz via the adc oscillator. table 1 the analog pll clock output frequencies the dividing factor q can be selected via the microcontroller. with this dividing factor q the user can select a range of adc clock signals allowing several different sample frequencies (see table 2). table 2 adc clock frequencies and sample frequencies based upon using the apll as a clock source table 3 adc clock frequencies and sample frequencies based upon using the oscad as a clock source notes 1. the oscillator frequency (and therefore the crystal) of oscad must be between 8.192 and 14.08 mhz. 2. the q factor can be 1, 2, 4 or 8. 3. sample frequencies below 5 khz and above 55 khz are not supported. fcode (1 and 0) apll clock frequency (mhz) 00 11.2896 01 8.1920 10 12.2880 11 11.2896 apll clock frequency (mhz) divide factor q adc clock frequency (mhz) sample frequency (khz) 8.1920 1 4.096 32 2 2.048 16 4 1.024 8 8 0.512 (not supported) 4 (not supported) 11.2896 1 5.6448 44.1 2 2.8224 22.05 4 1.4112 11.025 8 0.7056 5.5125 12.2880 1 6.144 48 2 3.072 24 4 1.536 12 8 0.768 6 oscad clock frequency (mhz) divide factor q adc clock frequency (mhz) sample frequency (khz) f osc (1) q (2) f osc /(2q) f osc /(256q) (3) 1999 may 10 12 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 the asynchronous digital-to-analog converter (adac) the adac receives audio data from the usb processor or from the digital i/o-bus. the adac is able to reconstruct the sample clock from the rate at which the audio samples arrive and handles the audio sound processing. after the processing, the audio signal is upsampled, noise-shaped and converted to analog output voltages capable of driving a line output. the adac consists of: a sample frequency generator (sfg) fifo registers an audio feature processing dsp two digital upsampling filters and a variable hold register a digital noise shaper (ns) a filter stream dac (fsdac) with integrated filter and line output drivers. the sample frequency generator (sfg) the sfg controls the timing signals for the asynchronous digital-to-analog conversion. by means of a digital pll, the sfg automatically recovers the applied sampling frequency and generates the accurate timing signals for the audio feature processing dsp and the upsampling filters. the lock time of the digital pll can be chosen (see table 8). while the digital pll is not in lock, the adac is muted. as soon as the digital pll is in lock, the mute is released as described in section soft mute control. first-in first-out (fifo) registers the fifo registers are used to store the audio samples temporarily coming from the usb processor or from the digital i/o input. the use of a fifo (in conjunction with the sfg) is necessary to remove all jitter present on the incoming audio signal. the sound processing dsp a dsp processes the sound features. the control and mapping of the sound features is explained in section controlling the playback features of the adac. depending on the sampling rate (f s ) the dsp knows four frequency domains in which the treble and bass are regulated. the domain is chosen automatically. table 4 frequency domains for audio processing by the dsp the upsampling ?lters and variable hold function after the audio feature processing dsp two upsampling filters and a variable hold function increase the oversampling rate to 128f s . the noise shaper a 3rd-order noise shaper converts the oversampled data to a noise-shaped bitstream for the fsdac. the in-band quantization noise is shifted to frequencies well above the audio band. the filter stream dac (fsdac) the fsdac is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. the filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. in this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. a post filter is not needed because of the inherent filter function of the dac. on-board amplifiers convert the fsdac output current to an output voltage signal capable of driving a line output. domain sample frequency (khz) 1 5 to 12 212to25 325to40 440to55 1999 may 10 13 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 usb endpoint description the UDA1325 has following six endpoints: usb control endpoint 0 usb control endpoint 1 usb status interrupt endpoint 1 usb status interrupt endpoint 2 isochronous data sink endpoint isochronous data source endpoint. table 5 endpoint description controlling the playback features controlling the playback features of the adac the exchange of control information between the microcontroller and the adac is accomplished through a serial hardware interface comprising the following pins: l3_data: microcontroller interface data line l3_mode: microcontroller interface mode line l3_clk: microcontroller interface clock line. see also the description of port 3 of the 80c51 microcontroller. information transfer through the microcontroller bus is organized in accordance with the so-called l3 format, in which two different modes of operation can be distinguished; address mode and data transfer mode. the address mode is required to select a device communicating via the l3-bus and to define the destination registers for the data transfer mode. data transfer for the UDA1325 can only be in one direction, from microcontroller to adac to program its sound processing features and other functional features. a ddress mode the address mode is used to select a device (in this case the adac) for subsequent data transfer and to define the destination registers. the address mode is characterized by l3_mode being low and a burst of 8 pulses on l3_clk, accompanied by 8 data bits on l3_data. data bits 0 and 1 indicate the type of the subsequent data transfer as shown in table 6. endpoint number endpoint index endpoint type direction max. packet size (bytes) 0 0 control (default) out 8 1in8 1 2 control out 8 3in8 2 4 interrupt in 8 3 5 interrupt in 8 4 6 isochronous out out 336 5 7 isochronous in in 336 1999 may 10 14 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 table 6 selection of data transfer type data bits 7 to 2 represent a 6-bit device address, with bit 7 being the msb and bit 2 the lsb. the address of the adac is 000101 (bits 7 to 2). in the event that the adac receives a different address, it will deselect its microcontroller interface logic. d ata transfer mode the selection preformed in the address mode remains active during subsequent data transfers, until the adac receives a new address command. the data transfer mode is characterized by l3_mode being high and a burst of 8 pulses on l3_clk, accompanied by 8 data bits. all transfers are bitwise, i.e. they are based on groups of 8 bits. data will be stored in the adac after the eight bit of a byte has been received. the principle of a multibyte transfer is illustrated in the figure below. p rogramming the sound processing and other features the sound processing and other feature values are stored in independent registers. the first selection of the registers is achieved by the choice of data transfer type. this is performed in the address mode, bits 1 and 0 (see table 6). the second selection is performed by bit 7 and/or bit 6 of the data byte depending of the selected data transfer type. data transfer type audio feature registers when the data transfer type audio feature registers is selected 4 audio feature registers can be selected depending on bits 7 and 6 of the data byte (see table 7). bit1 bit0 data transfer type 0 0 audio feature registers (volume left, volume right, bass and treble) 0 1 not used 1 0 control registers 1 1 not used n dbook, full pagewidth t halt address l3data l3clock l3mode address data byte #1 data byte #2 mgd018 1999 may 10 15 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 table 7 adac audio feature registers the sequence for controlling the adac audio feature registers via the l3-bus is given in the figure below. data transfer type control registers when the data transfer type control registers is selected 2 general control registers can be selected depending on bit 7 of the data byte (see table 7). the sequence for controlling the adac control registers via the l3-bus is given in the figure below. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 register 0 0 vr5 vr4 vr3 vr2 vr1 vr0 volume right 0 1 vl5 vl4 vl3 vl2 vl1 vl0 volume left 1 0 x bb4 bb3 bb2 bb1 bb0 bass 1 1 x tr4 tr3 tr2 tr1 tr0 treble d book, full pagewidth mgs270 0 bit 0 data_transfer_type l3_data (l3_mode = low) 0 1 0 1 device address = $5 0 0 0 bit 7 x bit 0 l3_data (l3_mode = high) x x x x register address left volume; treble right volume; bass x x x bit 7 l3_clk d book, full pagewidth mgs269 0 bit 0 data_transfer_type l3_data (l3_mode = low) 1 1 0 1 device address = $5 0 0 0 bit 7 x bit 0 l3_data (l3_mode = high) x x x x register address data of the control register x x x bit 7 l3_clk 1999 may 10 16 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 table 8 adac general control registers soft mute control when the mute (bit 1 of control register 0) is active for the playback channel, the value of the sample is decreased smoothly to zero following a raised cosine curve. there are 32 coefficients used to step down the value of the data, each one being used 32 times before stepping to the next. this amounts to a mute transition of 23 ms at f s = 44.1 khz. when the mute is released, the samples are returned to the full level again following a raised cosine curve with the same coefficients being used in reversed order. the mute, on the master channel is synchronized to the sample clock, so that operation always takes place on complete samples. register bit description value comment control register 0 0 reset adac 0 = not reset 1 = reset 1 soft mute control 0 = not muted 1 = mutes 2 synchronous/asynchronous 0 = asynchronous 1 = synchronous select 0 3 channel manipulation 0 = l -> l, r -> r 1=l->r, r->l 4 de-emphasis 0 = de-emphasis off 1 = de-emphasis on 6 and 5 audio mode 00 = ?at mode 01 = min. mode 10 = min. mode 11 = max. mode 7 selecting bit 0 control register 1 1 and 0 serial i 2 s-bus input format 00 = i 2 s-bus 01 = 16-bit lsb justi?ed 10 = 18-bit lsb justi?ed 11 = 20-bit lsb justi?ed 3 and 2 digital pll mode 00 = adaptive 01 = ?x state 1 10 = ?x state 2 11 = ?x state 3 select 00 4 digital pll lock mode 0 = adaptive 1 = ?xed select 1 6 and 5 digital pll lock speed 00 = lock after 512 samples 01 = lock after 2048 samples 10 = lock after 4096 samples 11 = lock after 16348 samples select 00 7 selecting bit 1 1999 may 10 17 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 volume control the volume of the UDA1325 can be controlled from 0 db down to - 60 db (in steps of 1 db). below - 60 db the audio signal is muted ( - db). the setting of 0 db is always referenced to the maximum available volume setting. independant volume control of the left and right channel is possible (balance control). table 9 volume settings right playback channel table 10 volume settings left playback channel vr5 vr4 vr3 vr2 vr1 vr0 volume (db) 0000000 0000010 000010 - 1 000011 - 2 000100 - 3 ... ... ... ... ... ... ... 111100 - 59 111101 - 60 111110 - 111111 - vl5 vl4 vl3 vl2 vl1 vl0 volume (db) 0000000 0000010 000010 - 1 000011 - 2 000100 - 3 ... ... ... ... ... ... ... 111100 - 59 111101 - 60 111110 - 111111 - 1999 may 10 18 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 treble control for the playback channel, treble can be regulated in three audio modes: minimum, flat and maximum mode. in flat mode the audio is not influenced. in minimum and maximum mode, the treble range is from 0 to 6 db in steps of 2 db. the programmable treble filter is implemented digitally and has a fixed corner frequency of 3000 hz for the minimum mode and 1500 hz for the maximum mode. because of the exceptional amount of programmable gain, treble should be used with adequate prior attenuation, using volume control. table 11 treble settings bass control for the playback channel, bass can be regulated in three audio modes: minimum, flat and maximum mode. in flat mode the audio is not influenced. in minimum mode the bass range is from 0 to approximately 14 db in steps of 1.5 db. in maximum mode, the bass range is from 0 to approximately 24 db in steps of 2 db. the programmable bass filters are implemented digitally and have a fixed corner frequency of 100 hz for the minimum mode and 75 hz for the maximum mode. because of the exceptional amount of programmable gain, bass should be used with adequate prior attenuation, using volume control. tr4 tr3 tr2 tr1 tr0 treble (db) flat set min. set max. set 00000000 00001000 00010000 00011000 00100022 00101022 00110022 00111022 01000044 01001044 01010044 01011044 01100066 01101066 01110066 01111066 ... ... ... ... ... 0 6 6 11111066 1999 may 10 19 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 table 12 bass boost settings de-emphasis de-emphasis is controlled by bit 4 of control register 0. the de-emphasis filter can be switched on or off. the digital de-emphasis filter is dimensioned to produce the de-emphasis frequency characteristics for the sample rate 44.1 khz. de-emphasis is synchronized to the sample clock, so that operation always takes place on complete samples. bb4 bb3 bb2 bb1 bb0 bass (db) flat set min. set max. set 00000000 00001000 00010000 00011000 0010001.11.7 0010101.11.7 0011002.43.6 0011102.43.6 0100003.75.4 0100103.75.4 0101005.27.4 0101105.27.4 0110006.89.4 0110106.89.4 0111008.411.3 0111108.411.3 100000 10.2 13.3 100010 10.2 13.3 10010011.9 15.2 10011011.9 15.2 101000 13.7 17.3 101010 13.7 17.3 101100 13.7 19.2 101110 13.7 19.2 110000 13.7 21.2 110010 13.7 21.2 110100 13.7 23.2 110110 13.7 23.2 ... ... ... ... ... 0 13.7 23.2 111110 13.7 23.2 1999 may 10 20 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 filter characteristics playback channel the overall filter characteristic of the UDA1325 in flat mode is given in fig.4 (de-emphasis off). the overall filter characteristic of the UDA1325 includes the filter characteristics of the dsp in flat mode plus the filter characteristic of the fsdac (f s = 44.1 khz) fig.4 overall filter characteristics of the UDA1325. handbook, full pagewidth mgm110 volume (db) f (khz) 10 20 30 40 50 60 70 80 90 100 0 - 160 - 120 - 80 - 40 - 140 - 100 - 60 - 20 - 0 1999 may 10 21 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 dsp extension port for enhanced playback audio processing an external dsp can be used for adding extra sound processing features via the i 2 s inputs and outputs of the digital i/o module. the UDA1325 supports the standard i 2 s-bus data protocol and the lsb-justified serial data input format with word lengths of 16, 18 and 20 bits. using the 4-pin digital i/o option the UDA1325 device acts as a master, controlling the bcko and wso signals. using the 6-pin digital i/o option gp2, gp3 and gp4 are output pins (master) and gp0, gp1 and gp5 are input pins (slave). the period of the wso signal is determined by the number of samples in the 1 ms frame of the usb. this implies that the wso signal does not have a constant time period, but is jittery. the characteristic timing of the i 2 s-bus signals is illustrated in figs 5 and 6. fig.5 timing of digital i/o input signals. handbook, full pagewidth mgk003 ws right lsb msb left bck data t f t r t h;ws t s;ws t bck(h) t bck(l) t cy t s;dat t h;dat 1999 may 10 22 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... b ook, full pagewidth lsb-justified format 16 bits lsb-justified format 18 bits lsb-justified format 20 bits left left left right right right 2 2 15 16 17 18 1 15 16 1 msb lsb b2 msb b2 b3 b4 b15 lsb b17 2 15 16 17 18 1 msb b2 b3 b4 lsb b17 2 15 16 17 18 19 20 1 msb b2 b3 b4 b5 b6 lsb b19 2 15 16 17 18 19 20 1 msb b2 b3 b4 b5 b6 lsb b19 2 15 16 1 msb lsb b2 b15 ws left right 3 2 1 3 2 1 msb b2 msb lsb lsb msb b2 > =8 > =8 bck data ws bck data ws bck data ws bck data input format i 2 s-bus mgk002 fig.6 input formats. 1999 may 10 23 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 port definition 80c51 port 1 table 13 port 1 of the 80c51 microcontroller port 3 table 14 port 3 of the 80c51 microcontroller 8 bit port 1 bit function low high comment 1.0 adac_error no error error 1.1 gp1 general purpose pins 1.2 gp2 1.3 gp3 1.4 gp4 1.5 gp5 1.6 scl i 2 c-bus 1.7 sda 8 bit port 3 bit function low high comment 3.0 asr_error no error error 3.1 psie_mmu_suspend no suspend suspend suspend input from usb interface during normal operation or input from restart circuit 3.2 gp0 (int0_n) general purpose pin 3.3 psie_mmu_int (int1_n) interrupt input from usb interface during normal operation or input from restart circuit 3.4 psie_mmu_ready 3.5 l3_mode 3.6 l3_clk 3.7 l3_data 1999 may 10 24 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 memory and register space 80c51 overview registers table 15 register location and recommended values after power-on reset table 16 special function register location address register reset value 0800h pga gain 09 0801h adif control 5c 1000h clock shop settings 00 1001h reset control and apll settings 00 1002h io selection register 01 1003h power control 00 2000h asr settings 8b 4000h data register psie 4001h command register psie address register reset value cpu registers 81h sp 82h dpl 83h dph d0h psw e0h acc f0h b interrupt registers a8h ie 00h b8h ip 00h timer 0 and timer 1 registers 88h t01con 00h 89h t01mod 00h 8ah t0l 00h 8bh t1l 00h 8ch t0h 00h 8dh t1h 00h pcon registers 87h pcon 00h interrupts the UDA1325 supports up to five (of maximal 7) interrupt sources. each interrupt source corresponds to an interrupt vector in the cpu program memory address space: source 0: vector 0003h external interrupt 0 (int0_n) source 1: vector 000bh timer 0 interrupt source 2: vector 0013h external interrupt 1 (int1_n) source 3: vector 001bh timer 1 interrupt source 4: vector 0023h uart interrupt (not present) source 5: vector 002bh timer 2 interrupt (not present) source 6: vector 0033h i 2 c interrupt. i nterrupt e nable register (ie) each interrupt source can be individually enabled or disabled by setting or clearing a bit in ie. this register also contains a global interrupt enable bit (ea) which can be cleared to disable all interrupts at once. port registers 80h p0 ffh 90h p1 ffh a0h p2 ffh b0h p3 ffh i 2 c registers (sio1 registers) d8h s1con 00h d9h s1sta dah s1dat dbh s1adr address register reset value 0 0 0 0 0 0 0 0 ex0 (vector 0003h)) et0 (vector 000bh)) ex1 (vector 0013h) et1 (vector 001bh) es0 (n.a.) et2 (n.a.) es1 (vector 0033h) ea 76543210 power on value 1999 may 10 25 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 internal registers table 17 pga gain registers table 18 adif control registers address register comments bit value 0800h pga gain register reserved 7 x pga input selection 6 0 (do not change it) pga gain right channel 5, 4 and 3 000 = - 3db 001 = 0 db 010 = 3 db 011=9db 100 = 15 db 101 = 21 db 110=27db 111=27db pga gain left channel 2, 1 and 0 000 = - 3db 001 = 0 db 010 = 3 db 011=9db 100 = 15 db 101 = 21 db 110=27db 111=27db address register comments bit value 0801h adif control register reserved 7 x number of bits per audio sample to be transmitted to the host 6 and 5 00 = reserved 01 = 8 bits audio samples 10 = 16 bits audio samples 11 = 24 bits audio samples mono/stereo selection 4 0 = mono 1 = stereo selection audio input recording channel 3 0 = digital serial audio input 1 = analog input selection high-pass ?lter of adif (dc-?lter) 2 0 = high-pass ?lter off 1 = high-pass ?lter on i 2 s-bus input serial input format recording channel 1 and 0 00 = i 2 s-bus 01 = 16-bit lsb justi?ed 10 = 18-bit lsb justi?ed 11 = 20-bit lsb justi?ed 1999 may 10 26 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 table 19 clock shop register table 20 reset control and apll register address register comments bit value 1000h clock shop settings selection adc clock source 7 0 = adc clock from apll 1 = adc clock from oscad divide factor q 6 and 5 00 = adc clock divided-by-1 01 = adc clock divided-by-2 10 = adc clock divided-by-4 11 = adc clock divided-by-8 clock adac 4 0 = enable 1 = disable clock 48 mhz internal 3 0 = enable 1 = disable clock recovered by psie 2 0 = enable 1 = disable adc clock 1 0 = enable 1 = disable oscad oscillator 0 0 = power on 1 = power off address register comments bit value 1001h reset control and apll settings fcode (1 and 0) clock frequency selection apll 7 and 6 00 = 256 44.1 khz 01 = 256 32 khz 10 = 256 48 khz 11 = 256 44.1 khz reserved 5 x reset adac 4 0 = reset off 1 = reset on reset mmu 3 0 = reset off 1 = reset on reset digital i/o-interface 2 0 = reset off 1 = reset on reset adif 1 0 = reset off 1 = reset on reserved 0 x 1999 may 10 27 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 table 21 i/o selection register table 22 power control register address register comments bit value 1002h i/o selection register microcontroller control on 48 mhz oscillator 7 0 = upc control disabled (48 mhz oscillator is enabled) 1 = upc control enabled audio format 6 and 5 00 = 4-pins i 2 s 01 = 6-pins i 2 s 10 = 3-pins i 2 s (only input) 11 = 3-pins i 2 s (only input) gp4 i/o if bit0 = 1 4 0 = output 1 = input gp3 i/o if bit0 = 1 3 0 = output 1 = input gp2 i/o if bit0 = 1 2 0 = output 1 = input gp1 i/o if bit0 = 1 1 0 = output 1 = input gp4 to gp1 function 0 0 = i 2 s usage 1 = general purpose usage address register comments bit value 1003h power control register analog modules suspend input selection for p3.1 of the microcontroller 7 0 = suspend from usb interface connected to p3.1 during normal operation 1 = suspend from restart circuit connected to p3.1 (e.g. after power-down) interrupt input selection for p3.3 (int1_n) of the microcontroller 6 0 = interrupt from usb interface connected to p3.3 during normal operation 1 = interrupt from restart circuit connected to p3.3 (e.g. after power-down) power apll 5 0 = power on 1 = power off power fsdac 4 0 = power on 1 = power off power adc left 3 0 = power on 1 = power off power adc right 2 0 = power on 1 = power off power pga left 1 0 = power on 1 = power off power pga right 0 0 = power on 1 = power off 1999 may 10 28 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 table 23 asr control register start-up behaviour and power management start-up of the UDA1325 after power-on (of v dda1 ), an internal power-on reset signal becomes high after a certain rc time. this rc time is created by using the internal resistor (2 50 k w ) divider for creating the reference voltage for the fsdac in combination with the capacitor connected externally to the v refda pin. the fsdac and the internal resistor divider are supplied by v dda1 and v ssa1 . the rc time can be calculated using r = 25000 w and c = c ref . during 20 ms after power-on reset becomes high the UDA1325 has to initiate the internal registers. during this initialisation, the user should prevent indicating the connected status to the usb-host. this can be done by forcing the dp-line low (i.e. via one of the gp pins). power management the total current drawn from the usb supply (for i.e. bus-powered operation of the UDA1325 application) must be less than 500 m a in suspend mode. in order to reach that low current target, the total power dissipation of the UDA1325 can be reduced by disabling all internal clocks and switching off all internal analog modules. important note: in order to make use of power reduction (power-down mode) and be able to restart after power-down, a number of precautions must be taken! address register comments bit value 2000h asr control register robust word clock 7 0 = off (not recommended) 1 = on (recommended) serial i 2 s-bus output format digital i/o interface 6 and 5 00 = i 2 s-bus 01 = 16-bit lsb justi?ed 10 = 18-bit lsb justi?ed 11 = 20-bit lsb justi?ed phase inversion (on right mono output) 4 0 = mono phase inversal off 1 = mono phase inversal on bits per sample modi 3 and 2 00 = reserved 01 = 8-bit audio 10 = 16-bit audio 11 = 24-bit audio mono or stereo operation 1 0 = mono 1 = stereo asr register start-up mode 0 0 = stop (e.g. at alternate setting with bandwidth equal to zero) 1=go 1999 may 10 29 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 a t initialisation time bit 7of the power control register (mux_ctrl_suspend) must be set to 1, in order to connect the clk_on of the usb processor with p3.1 of the microcontroller bit 6 of the power control register (mux_ctrl_int1) must be set to 0, in order to connect the psie_mmu_int output pin of the usb processor with p3.3 (int1_n) of the microcontroller bit 7of the i/o selection register must be set to 1, in order to enable the power-on control of the 48 mhz crystal oscillator automatically by the microcontroller. i n normal operation mode in normal operation working mode, a suspend can be initiated by the falling edge of the clk_on output signal of the usb processor. this falling edge comes about 2 ms after the rising edge of the psie_mmu_suspend output signal of the usb processor. at this moment, several actions should be taken by the microcontroller: all analog modules of the UDA1325 must be switched off; this can be done by setting bits 5 to 0 of the power control register to 1 and bit 0 of the clock shop register to 1 bit 6 of the power control register (mux_ctrl_int1) must be set to 1, in order to awake from power-down by the clk_on signal of the usb processor put all gp pins in the high or low state (depending of how they are used in the UDA1325 application) put the microcontroller in power-down mode. this can be done via the pcon register of the microcontroller. this results in an automatically switching off the 48 mhz crystal oscillator and with that all internal clocks (if they are enabled). on the rising edge of the clk_on output signal, the 48 mhz crystal oscillator will be switched on automatically and with that all internal clocks (if they are enabled). at the same time, a counter starts counting for 2048 clock cycles (170 m s). this time is necessary for stabilising the 48 mhz clock of the 48 mhz crystal oscillator. when the counter reaches its end value (after 2048 cycles), a rising edge will be detected on the p3.3 (int1_n) of the microcontroller. at this moment, following actions should be taken by the microcontroller: the power-down mode of the microcontroller must be switched off re-initialise all gp pins all analog modules of the UDA1325 must be switched on; this can be done by setting bits 5 to 0 of the power control register to 0 and bit 0 of the clock shop register to 0 bit 6 of the power control register (mux_ctrl_int1) must be set to 0, in order to connect the psie_mmu_int output pin of the usb processor again with p3.3 (int1_n) of the microcontroller. the UDA1325 is now back in its normal operation mode and can be put back in power reduction mode by the falling edge of the clk_on signal of the usb processor. 1999 may 10 30 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 command summary command name recipient coding data phase initialization commands set address/enable device d0h write 1 byte read address/enable device d0h read 1 byte set endpoint enable device d8h write 1 byte read endpoint enable device d8h read 1 byte set mode device f3h write 1 byte data ?ow commands read interrupt register device f4h read 1 byte select endpoint control out 00h read 1 byte (optional) control in 01h read 1 byte (optional) other endpoints 00h + endpoint index read 1 byte (optional) get endpoint status control out 40h read 1 byte control in 41h read 1 byte other endpoints 40h + endpoint index read 1 byte set endpoint status control out 40h write 1 byte control in 41h write 1 byte other endpoints 40h + endpoint index write 1 byte read buffer selected endpoint f0h read n bytes write buffer selected endpoint f0h write n bytes acknowledge setup selected endpoint f1h none clear buffer selected endpoint f2h none validate buffer selected endpoint fah none general commands read current frame number f5h read 1 or 2 bytes 1999 may 10 31 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 command descriptions command procedure this chapter describes the commands that can be used by the microcontroller to control the usb processor. there are three basic types of commands: initialization commands data flow commands general commands. a command is represented by an 8 bit code. it can be followed by one or more data write cycles or one or more read cycles or a combination. the psie_mmu_ready output connected to port 3.4 of the microcontroller indicates that the previous action (command write, data read or data write) has completed. a new action can only be initiated if psie_mmu_ready is true. the data is valid from the moment psie_mmu_ready becomes true. the psie contains a number of interrupt registers, one for each endpoint. every time a transition occurs, the interrupt flag for the involved endpoint is set. the psie_mmu_int connected to port 3.3 is an or function of all interrupt registers. initialization commands initialization commands are used during the enumeration process of the usb network. they are used to set the usb assigned address, enable endpoints and select the configuration of the device. s et address / enable command: d0h. data: write 1 byte. the set address/enable command is used to set the usb assigned address and enable the function. the device always powers up disabled and should be enabled after a bus reset. 0 address enable 0 1 2 3 4 5 6 7 0 00 0000 power on value table 24 r ead address / enable command: d0h. data: read 1 byte. the read address/enable command is used to read the usb assigned address and the enable bit of the device. the format of the data phase is the same as for the set address/enable command. s et endpoint enable command: d8h. data: write 1 byte. the set endpoint enable command is used to set the enable bits for the non default endpoints. if the enable bit is 1, the non default endpoints are enabled, if 0, the non default endpoints are disabled. the function then only responds to the default control endpoint. after bus reset, the enable bit is set to 0. r ead endpoint enable command: d8h. data: read 1 byte. the read endpoint enable command is used to read the enable bit for the non default endpoints of the function. the format of the data phase is the same as for the set endpoint enable command. s et mode command: f3h. data: write 1 byte. bit description address the value written becomes the device address enable a 1 enables this function xxxxxxx 0 enable reserved 76543210 power on value 1999 may 10 32 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 reset value: gives the value of the bits after power-on reset. bus reset: a f indicates that the value of the bit is not changed during a bus reset. a t indicates that during a bus reset, the bit is reset to its reset value. table 25 data ?ow commands data flow commands are used to manage the data transmission between the usb endpoints and the host. much of the data flow is initiated via the interrupt to the microcontroller. the microcontroller uses these commands to access the endpoint buffers and determine whether the endpoint buffers have valid data. r ead interrupt register command: f4h. data: read 1 byte. the read interrupt register command returns the value of the interrupt register. every time a packet is received or transmitted, an interrupt will be generated and a flag specific to the physical endpoint will be set in the interrupt register. reading the status of the endpoint will clear the flag. bit description isoout iso out endpoint can be used isoin iso in endpoint can be used intisoout allow interrupt from iso out endpoint intisoin allow interrupt from iso in endpoint errordebugmode setting chip in debug mode alwayspllclock the pll clock must keep on running t t f f t t t t isoout isoin intisoout intisoin errordebugmode alwayspllclock reserved reserved 76543210 bus reset 1 1 1 1 1 1 0 0 reset value an interrupt is also generated after a bus reset. when the interrupt register consists of all zeros, and an interrupt was generated, there was a bus reset. the interrupt is cleared when the interrupt register is read. s elect endpoint command: 00h + endpoint index. data: optional read 1 byte. the select endpoint command initializes an internal pointer to the start of the selected buffer. optionally, this command can be followed by a data read. bit 0 is low if the buffer is empty and high if the buffer is full. there is one command for every endpoint. g et endpoint status command: 40h + endpoint index. data: read 1 byte. the get endpoint status command is followed by one data read that returns the status of the last transaction of the selected endpoint. this command also resets the corresponding interrupt flag in the interrupt register, and clears the status, indicating that it was read. there is one command for every endpoint. 0 0 0 0 0 0 0 0 control out control in endpoint 1 out endpoint 1 in endpoint 2 in endpoint 3 in endpoint 4 out endpoint 5 in 76543210 power on value xxxxxxx 0 full/empty reserved 76543210 power on value 0 0 00 0 data receive/transmit error code setup packet data 0/1 packet previous status not read 000 76543210 power on value 1999 may 10 33 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 table 26 error codes table 27 error code result 0000 no error 0001 pid encoding error; bits 7 to 4 in the pid token are not the inversion of bits 3 to 0 0010 pid unknown; pid encoding is valid, but pid does not exist 0011 unexpected packet; packet is not of the type expected (token, data or acknowledge), or setup token received on non-control endpoint 0100 token crc error 0101 data crc error 0110 time out error 0111 babble error 1000 unexpected end-of-packet 1001 sent or received nak 1010 sent stall, a token was received, but the endpoint was stalled 1011 over?ow error, the received data packet was larger then the buffer size of the selected endpoint 1100 sent empty packet (iso only) 1101 bitstuff error 1110 error in sync 1111 wrong data pid bit description data receive/transmit a 1 indicates data has been received or transmitted successfully error code see table 26 setup packet a 1 indicates the last received packet had a setup token (this will always read 0 for in buffers) data 0/1 packet a 1 indicates the last received packet had a data 1 pid previous status not read a 1 indicates a second event occurred before the previous status was read s et endpoint status command: 40h + endpoint index. data: write 1 byte. this command is used to stall or unstall an endpoint. only the least significant bit has a meaning. when the stalled bit is equal to 1, the endpoint is stalled, when equal to 0, the endpoint is unstalled. there is one command for every endpoint. a stalled control endpoint is automatically unstalled when it receives a setup token, regardless of the contents of the packet. if the endpoint should stay in stalled state, the microcontroller should restall it. when a stalled endpoint is unstalled, it is also re-initialized. this means that its buffer is flushed and the next data pid that will be sent or expected (depending on the direction of the endpoint) is data0. r ead buffer command: f0h. data: read n bytes (max. 10). the read buffer command is followed by a number of data reads, which returns the contents of the selected endpoint data buffer. after each read, the internal buffer pointer is incremented by 1. the buffer pointer is not reset to the buffer start by the read buffer command. this means that reading a buffer can be interrupted by any other command (except for select endpoint). x stalled reserved 0 1 2 3 4 5 6 7 x xx xxx power on value 0 1999 may 10 34 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 the data in the buffer are organized as follows: byte 0: transfer successful, number of data bytes (msb) byte 1: number of data bytes (lsb) byte 2: data byte 0 byte 3: data byte 1 byte 4: data byte 2 byte 5: data byte 3 byte 6: data byte 4 byte 7: data byte 5 byte 8: data byte 6 byte 9: data byte 7. bytes 0 and 1 indicate the number of bytes in the buffer. byte 0 is the most significant byte (msb). byte 1 is the least significant byte (lsb). only bits 1 and 0 of byte 0 are used in the number of bytes indication. bit 7 of byte 0 indicates if the transaction was successful (bit 7 is 1 if the transaction was successful). bits 6 to 2 of byte 0 are reserved. w rite buffer command: f0h. data: write n bytes (max. 10). the write buffer command is followed by a number of data writes, which load the endpoint buffer. after each write, the internal buffer pointer is incremented by 1. the buffer pointer is not reset to the buffer start by the write buffer command. this means that writing a buffer can be interrupted by any other command (except for select endpoint). the data must be organized in the same way as described in the read buffer command. bits 7 to 2 of byte 0 are reserved and must be filled with zeros. a cknowledge s etup command: f1h. data: none. the arrival of a setup packet flushes the in buffer and disables the validate buffer and clear buffer commands for both in and out endpoints. the microcontroller needs to re-enable these commands by the acknowledge setup command. this ensures that the last setup packet stays in the buffer and no packet can be sent back to the host until the microcontroller has acknowledged explicitly that it has seen the setup packet. if the microcontroller is reading the data from a setup packet, and a new setup packet arrives, the device must accept this new setup packet. so the data, currently being read by the microcontroller, is overwritten with the new packet. on the arrival of the new packet, the commands validate buffer and clear buffer are disabled. if the microcontroller has finished reading the data from the buffer, it will try to clear the buffer. the device will ignore this command, so the new setup packet in the buffer is not cleared. the microcontroller will now detect the interrupt of the new setup packet and will start reading the new data in the buffer. a setup token can be followed by an in token. after the setup token, the microcontroller will start filling the in buffer. a setup token will clear the in buffer. this avoids the following problem: after a setup token, the microcontroller fills the in buffer. if the setup token is followed by a setup token and shortly followed by an in token, the device will send the contents of the in buffer to the host. the in buffer was filled after the first setup token. that is why after a setup token the in buffer is cleared. if the microcontroller is still filling the buffer when the second setup token arrives, the setup token will clear the in buffer. if the microcontroller has filled the in buffer, it will validate the buffer. so clearing the in buffer on receiving a setup token is not enough. if a setup token is received, the device will also disable the validate buffer command for the in buffer. if the microcontroller needs to fill the buffer after a setup token, the command acknowledge setup command must be sent to enable the validate buffer command. c lear buffer command: f2h. data: none. when a packet is received completely, an internal endpoint buffer full flag is set. all subsequent packets will be refused by returning a nack to the host. when the microcontroller has read the data, it should free the buffer by the clear buffer command. when the buffer is cleared, new packets will be accepted. 1999 may 10 35 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 v alidate buffer command: fah. data: none. when the microcontroller has written data into an in buffer, it should set the buffer full flag by the validate buffer command. this indicates that the data in the buffer are valid and can be sent to the host when the next in token is received. general commands r ead current frame number command: f5h. data: read 1 or 2 bytes. this command is followed by one or two data reads and returns the frame number of the last successfully received sof. the frame number is eleven bits wide. the frame number is returned least significant byte first. in case the user is only interested in the lower 8 bits of the frame number only the first byte needs to be read. i 2 c master/slave interface the i 2 c module implements a master/slave i 2 c-bus interface with integrated shift register, shift timing generation and slave address recognition. it is compliant to the i 2 c-bus specification ic20/jan92. i 2 c standard mode (100 khz scl) and fast mode (400 khz) are supported. low speed mode and extended 10 bit addressing are unsupported. characteristics of the i 2 c-bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to v dde via a pull-up resistor. the timing definition of the i 2 c-bus is given in fig.7. programmers view for a detailed description of the i 2 c-bus protocol refer to philips integrated circuits data handbook ic20, 8xc552. the programmers view of the i 2 c library function is -with one exception- identical to that of the 8xc552 microcontroller. only the bit rate frequency selection in s1con and the handling of the timer 1 overflow information deviates to accommodate 400 khz operation. s1con register the cpu can read from and write to this 8-bit sfr. two bits are effected by the sio1 hardware: the si bit is set when a serial interrupt is requested, and the sto bit is cleared when a stop condition is present on the i 2 c-bus. the sto bit is also cleared when ens1 = 0. reset initializes s1con to 00h. cr2, 1 and 0- the clock rate bits these three bits determine the serial clock frequency when sio1 is in a master mode. the various serial rates are shown in table 28. table 28 serial clock rates (scl line) when the cr bits are 111, the maximum bit rate for the data transfer will be derived from the timer 1 overflow rate divided by 2 (i.e. every time the timer 1 overflows, the scl signal will toggle). cr2 cr1 cr0 i 2 c bit frequency (khz) 0 0 0 1200 0 0 1 600 0 1 0 400 0 1 1 300 1 0 0 150 1 0 1 100 110 75 1 1 1 3.9 ... 501 0 0 0 0 0 0 0 0 cr0 cr1 aa si sto sta ens1 cr2 76543210 power on value 1999 may 10 36 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... handbook, full pagewidth mbc611 p s sr p t su;sto t sp t hd;sta t su;sta t su;dat t f t high t r t hd;dat t low t hd;sta t buf sda scl fig.7 definition of timing of the i 2 c-bus. 1999 may 10 37 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistor. 2. equivalent to discharging a 200 pf capacitor through a 2.5 m h series conductor. thermal characteristics recommended operating conditions symbol parameter conditions min. typ. max. unit all digital i/os v i/o dc input/output voltage range - 0.5 - v dde v i o output current v dde = 5.0 v -- 4ma temperature values t j junction temperature 0 - 125 c t stg storage temperature - 55 - +150 c t amb operating ambient temperature 0 25 70 c electrostatic handling v es electrostatic handling note 1 - 3000 - +3000 v note 2 - 300 - +300 v symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient UDA1325ps in free air 48 k/w UDA1325h in free air 48 k/w symbol parameter min. typ. max. unit v dde supply voltage periphery (i/o) 4.75 5.0 5.25 v v dd supply voltage (core) 3.0 3.3 3.6 v v i dc input voltage range for d+ and d - 0.0 - v dd v for vinl and vinr - 0.5v dd - v for digital i/os 0.0 - v dde v 1999 may 10 38 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 dc characteristics v dde = 5.0 v; v dd = 3.3 v; t amb =25 c; f osc = 48 mhz; f s = 44.1 khz; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v dde digital supply voltage periphery 4.75 5.0 5.25 v v ddi digital supply voltage core 3.0 3.3 3.6 v v dda1 analog supply voltage 1 3.0 3.3 3.6 v v dda2 analog supply voltage 2 3.0 3.3 3.6 v v dda3 analog supply voltage 3 3.0 3.3 3.6 v v ddo operational ampli?er supply voltage 3.0 3.3 3.6 v v ddx crystal oscillator supply voltage 3.0 3.3 3.6 v i dde digital supply current periphery note 1 - 3.7 - ma i ddi digital supply current core - 39.0 - ma i dda1 analog supply current 1 - 3.6 - ma i dda2 analog supply current 2 - 8.0 - ma i dda3 analog supply current 3 - 0.9 9.0 (2) ma i ddo operational ampli?er supply current - 3.0 - ma i ddx crystal oscillator supply current - 1.2 13.0 (3) ma p tot total power dissipation - 200 - mw p ps total power dissipation in power saving mode note 4 - 1.2 - mw inputs/outputs d+ and d - v i static dc input voltage - 0.5 - v ddi v v o(h) static dc output voltage high r l =15k w connected to gnd 2.8 - 3.6 v v o(l) static dc output voltage low r l = 1.5 k w connected to v dd -- 0.3 v ? i lo ? high impedance data line output leakage current -- 10 m a v i(diff) differential input sensitivity 0.2 -- v v cm(diff) differential common mode range 0.8 - 2.5 v v se(r)(th) single-ended receiver threshold voltage 0.8 - 2.0 v c in transceiver input capacitance pin to gnd -- 20 pf digital input pins v il low-level input voltage -- 0.3v dde v v ih high-level input voltage 0.7v dde - v dde v ? i li ? input leakage current -- 1 m a c i input capacitance -- 5pf 1999 may 10 39 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 notes 1. this value depends strongly on the application. the specified value is the typical value obtained using the application diagram as illustrated in fig.8. 2. at start-up of the oscad oscillator. 3. at start-up of the osc48 oscillator. 4. exclusive the idde current which depends on the components connected to the i/o pins. pga and adc v ref(ad) reference voltage pga and adc - 0.5v dda2 - v v ref(adc)(pos) positive reference voltage of the adc - v dda2 - v v ref(adc)(neg) negative reference voltage of the adc - 0.0 - v v i(pga) dc input voltage vinl and vinr of the pga - 0.5v dda2 - v r i(pga) dc input resistance at vinl and vinr of the pga - 12.5 - k w filter stream dac v ref(da) reference voltage dac - 0.5v dda1 - v v o(cm) common mode output voltage - 0.5v dda1 - v r o(vout) output resistance at voutl and voutr - 11 -w r o(l) output load resistance 2.0 -- k w c o(l) output load capacitance -- 50 pf symbol parameter conditions min. typ. max. unit 1999 may 10 40 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 ac characteristics v dde = 5.0 v; v ddi = 3.3 v; t amb =25 c; f osc = 48 mhz; f s = 44.1 khz; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit driver characteristics d+ and d - (full-speed mode) f o(s) audio sample output frequency 5 - 55 khz t r rise time c l =50pf 4 - 20 ns t f fall time c l =50pf 4 - 20 ns t rf(m) rise/fall time matching (t r /t f )90 - 110 % v cr output signal crossover voltage 1.3 - 2.0 v r o(drive) driver output resistance steady-state drive 28 - 43 w data source timings d+ and d - (full-speed mode) f i(s) audio sample input frequency 5 - 55 khz f fs(d) full speed data rate 11.97 12.00 12.03 mbits/s t fr(d) frame interval 0.9995 1.0000 1.0005 ms t j1(diff) source differential jitter to next transition - 3.5 0.0 +3.5 ns t j2(diff) source differential jitter for paired transitions - 4.0 0.0 +4.0 ns t w(eop) source end of packet width 160 - 175 ns t eop(diff) differential to end of packet transition skew - 2.0 - +5.0 ns t jr1 receiver data jitter tolerance to next transition - 18.5 0.0 +18.5 ns t jr2 receiver data jitter tolerance for paired transitions - 9.0 0.0 +9.0 ns t eopr1 end of packet width at receiver must reject as end of packet 40 -- ns t eopr2 end of packet width at receiver must accept as end of packet 82 -- ns serial input/output data timing f s system clock frequency - 12 - mhz f i(ws) word selection input frequency 5 - 55 khz t r rise time -- 20 ns t f fall time -- 20 ns t bck(h) bit clock high time 55 -- ns t bck(l) bit clock low time 55 -- ns t s;dat data set-up time 10 -- ns t h;dat data hold time 20 -- ns t s;ws word selection set-up time 20 -- ns t h;ws word selection hold time 10 -- ns 1999 may 10 41 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 sda and scl lines for 100 khz i 2 c devices f scl scl clock frequency 0 - 100 khz t buf bus free time between a stop and start condition 4.7 --m s t hd;sta hold time (repeated) start condition 4.0 --m s t low low period of the scl clock 4.7 --m s t high high period of the scl clock 4.0 --m s t su;sta set-up time for a repeated start condition 4.7 --m s t su;sto set-up time for stop condition 4.0 --m s t hd;dat data hold time 5.0 --m s t su;dat data set-up time 250 -- ns t r rise time of both sda and scl signals -- 1000 ns t f fall time of both sda and scl signals -- 300 ns c l(bus) capacitive load for each bus line -- 400 pf oscillator 1 (system clock) f osc oscillator frequency - 48 - mhz d duty factor - 50 - % g m transconductance 12.8 22.1 30.2 ms r o output resistance 0.6 1.1 2.3 k w c i(xtal1a) parasitic input capacitance xtal1a 4.5 4.8 5.2 pf c i(xtal2a) parasitic input capacitance xtal2a 4.1 4.6 5.0 pf i start start-up current 3.7 7.6 13.0 ma oscillator 2 (for adc clock) f osc oscillator frequency 8.192 - 14.08 mhz d duty cycle - 50 - % g m transconductance 8.1 13.6 18.1 ma/v r o output resistance 1.3 2.0 4.0 k w c i(xtal1b) parasitic input capacitance xtal1b 5.0 5.4 5.7 pf c i(xtal2b) parasitic input capacitance xtal2b 4.1 4.6 5.0 pf i start start-up current 2.4 5.0 8.4 ma symbol parameter conditions min. typ. max. unit 1999 may 10 42 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 analog pll (for adc clock) f clk(pll) pll clock frequency 8.1920 11.2896 12.2880 mhz d duty factor - 50 - % t strt(po) start-up time after power-on -- 10 ms power-on reset t su(po) power-on set-up-time note 1 25c ref (2) -- ms pga and adc v i(fs)(rms) full-scale input voltage (rms value) pga gain = - 3db - 1414 (3) - mv pga gai n=0db - 1000 - mv pga gai n=3db - 708 - mv pga gai n=9db - 355 - mv pga gain = 15 db - 178 - mv pga gain = 21 db - 89 - mv pga gain = 27 db - 44 - mv c i(pga) input capacitance of the pga -- 20 pf (thd + n)/s total harmonic distortion plus noise-to-signal ratio f s = 44.1 khz at input signal of 1 khz; pga gain = 0 db; note 4 v i (0 db) 1.0 v (rms) -- 85 - 80 db - 0.0056 0.01 % v i ( - 60 db) -- 30 - 20 db - 3.2 10.0 % s/n signal to noise ratio v i = 0.0 v 90 95 - dba a ct crosstalk between channels pga gai n=0db - 100 - db f s sample frequency (128f s ) 0.640 - 7.04 mhz ol digital output level pga gai n=0db, v i = 1 v (rms) -- 2.0 - dbfs symbol parameter conditions min. typ. max. unit 1999 may 10 43 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 notes 1. strongly depends on the external decoupling capacitor connected to v ref(da) . 2. c ref in m f. 3. although a level of 1.414 v (rms) would be required to optimal drive the adc in this gain setting, this level can not be used. due to the 3.3 v supply voltage input, signals of 1.17 v (rms) and higher will result in clipping. 4. measured with the apll as adc clock source. 5. measured with i 2 s-bus input as digital source. filter stream dac res resolution 16 -- bits v o(fs)(rms) full-scale output voltage (rms value) v dd = 3.3 v - 0.66 - v svrr supply voltage ripple rejection at v dda and v ddo f ripple = 1 khz v ripple(p-p) = 0.1 v - 60 - db ?d v o ? channel unbalance maximum volume - 0.03 - db a ct crosstalk between channels r l =5k w- 95 - db (thd + n)/s total harmonic distortion plus noise-to-signal ratio f s = 44.1 khz; r l =5k w ; note 5 at input signal of 1 khz (0 db) -- 90 - 80 db - 0.0032 0.01 % at input signal of 1 khz ( - 60 db) -- 30 - 20 db - 3.2 10 % s/n signal-to-noise ratio at bipolar zero a-weighting at code 0000h 90 95 - db symbol parameter conditions min. typ. max. unit 1999 may 10 44 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 application information fig.8 application diagram UDA1325h (continued in fig.9). handbook, full pagewidth 17 gp0/bcki 15 gp5/wsi 13 gp1/di 6 d - 8 d + 12 v dde 11 v sse 9 v ddi 10 38 39 v ssi UDA1325h + v d 100 nf (63 v) 100 nf (63 v) c27 c26 r25 1 w l3 blm32a07 + v c + v d + v c + v a 100 nf (63 v) 100 nf (63 v) c24 c25 r17 1 w l2 blm32a07 blm32a07 12 pf (63 v) c37 12 pf (63 v) c38 + v a 100 nf (63 v) 47 m f (16 v) c34 c38 r35 1 w + v c 25 xtal1b 26 xtal2b r48 1.5 k w 47 vinr r7 22 w r16 22 w 61 bck 59 ws 57 da x4 digital input playback digital input recording bcki wsi di bck ws da c18 22 pf (63 v) c17 22 pf (63 v) c16 10 nf (50 v) 1 l1 8 2 7 3 6 45 v dda1 v ssa1 42 44 + v a 100 nf (63 v) 47 m f (16 v) c32 c21 r27 1 w v dda2 v ssa2 1 53 xtal2a 54 xtal1a 10 nf (63 v) c44 l5 1.5 m h v usb c47 100 m f (16 v) c46 100 m f (16 v) c45 100 m f (16 v) c6 18 pf (50 v) c5 18 pf (50 v) 10 nf (50 v) c15 x1 48 mhz adc xtal l8 blm32a07 l7 blm32a07 l6 v d(ext) v a(ext) gnd mgm760 4 3 2 1 c8 47 m f (16 v) 43 vinl c22 47 m f (16 v) analog input recording 1999 may 10 45 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 fig.9 application diagram UDA1325h (continued from fig.8). handbook, full pagewidth r28 4.7 k w mgm761 56 p0.0 58 p0.1 60 p0.2 62 p0.3 64 p0.4 3 p0.5 5 p0.6 7 p0.7 50 ale 14 p2.0 16 p2.1 18 p2.2 20 p2.3 22 p2.4 23 p2.5 21 sda 19 scl 31 psen 18 17 14 1 a0 2 a1 3 a2 4 v ss 8 v dd 7 ptc 6 scl 5 sda 13 8 7 4 3 11 le 2 gp4/bcko 1 gp3/wso 63 28 gp2/do 36 rtcb 35 tc 4 shtcb v ddx 24 v ssx 32 v ddo 33 v sso 1 19 16 15 12 9 6 5 2 oe 74hct373d d1 d2 d4 UDA1325h pcf85116-3 10 a0 9 a1 8 a2 7 a3 6 a4 4 a6 5 a5 3 a7 24 a9 25 a8 21 a10 2 11 12 13 15 16 17 18 19 28 14 a12 23 a11 o0 o1 o2 o3 o4 o5 o6 o7 eepm27128 26 a13 22 oe 48 ea 20 ce 27 pgm 1 v pp + v d + v d + v c 100 nf (63 v) 100 nf (63 v) c18 c28 r26 1 w l13 blm32a07 + v a 100 nf (63 v) 47 m f (16 v) c39 c33 r43 1 w 40 v ref(da) 34 voutl r38 10 k w r39 10 k w bcko wso do 1 2 (i 2 c-bus) (internal rom) (external rom) c35 r20 1 w 47 m f (16 v) c48 47 m f (16 v) 37 voutr c41 47 m f (16 v) c29 100 nf (63 v) c36 100 nf (63 v) 41 v ref(ad) c31 47 m f (16 v) c28 100 nf (63 v) + v d + v d 1 2 3 j3 + v d v cc gnd c25 100 nf (50 v) 20 10 + v d v cc gnd c24 100 nf (50 v) 52 55 + v a 100 nf (63 v) 47 m f (16 v) c7 c19 r10 1 w v dda3 v ssa3 51 49 + v a 100 nf (63 v) c11 r8 1 w vrp vrn digital output playback analog output playback d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 1999 may 10 46 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... d book, full pagewidth 16 gp0/bcki 15 gp5/wsi 14 gp1/di 8 d - 9 d + 13 v dde 12 v sse 10 v ddi 11 29 30 v ssi UDA1325ps + v d 100 nf (63 v) 100 nf (63 v) c27 c26 r25 1 w l3 blm32a07 + v c + v d + v c + v a 100 nf (63 v) 100 nf (63 v) c24 c25 r17 1 w l2 blm32a07 blm32a07 12 pf (63 v) c37 12 pf (63 v) c38 + v a 100 nf (63 v) 47 m f (16 v) c34 c38 r35 1 w + v c 20 xtal1b 21 xtal2b r48 1.5 k w 36 vinr r7 22 w r16 22 w 3 bck 2 ws 1 da x4 digital input playback digital input recording bcki wsi di bck ws da c18 22 pf (63 v) c17 22 pf (63 v) c16 10 nf (50 v) 1 l1 8 2 7 3 6 45 v dda1 v ssa1 33 35 + v a 100 nf (63 v) 47 m f (16 v) c32 c21 r27 1 w v dda2 v ssa2 1 40 xtal2a 41 xtal1a 10 nf (63 v) c44 l5 1.5 m h v usb c47 100 m f (16 v) c46 100 m f (16 v) c45 100 m f (16 v) c6 18 pf (50 v) c5 18 pf (50 v) 10 nf (50 v) c15 x1 48 mhz adc xtal l8 blm32a07 l7 blm32a07 l6 v d(ext) v a(ext) gnd 4 3 2 1 c8 47 m f (16 v) 34 vinl c22 47 m f (16 v) analog input recording mgs271 18 sda 17 scl 1 a0 2 a1 3 a2 4 v ss 8 v dd 7 ptc 6 scl 5 sda 6 gp4/bcko 5 gp3/wso 4 22 gp2/do 27 rtcb 26 tc 7 shtcb v ddx 19 v ssx 23 v ddo 24 v sso d4 pcf85116-3 + v c 100 nf (63 v) 100 nf (63 v) c18 c28 r26 1 w l13 blm32a07 + v a 100 nf (63 v) 47 m f (16 v) c39 c33 r43 1 w 31 v ref(da) 25 voutl r38 10 k w r39 10 k w bcko wso do 1 2 (i 2 c-bus) c35 r20 1 w 47 m f (16 v) c48 47 m f (16 v) 28 voutr c41 47 m f (16 v) c29 100 nf (63 v) c36 100 nf (63 v) 32 v ref(ad) c31 47 m f (16 v) c28 100 nf (63 v) + v d + v d 39 42 + v a 100 nf (63 v) 47 m f (16 v) c7 c19 r10 1 w v dda3 v ssa3 38 37 + v a 100 nf (63 v) c11 r8 1 w vrp vrn digital output playback analog output playback fig.10 application diagram UDA1325ps. 1999 may 10 47 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 package outlines unit b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm dimensions (mm are the original dimensions) sot270-1 90-02-13 95-02-04 b max. w m e e 1 1.3 0.8 0.53 0.40 0.32 0.23 38.9 38.4 14.0 13.7 3.2 2.9 0.18 1.778 15.24 15.80 15.24 17.15 15.90 1.73 5.08 0.51 4.0 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 42 1 22 21 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z a max. 12 a min. a max. sdip42: plastic shrink dual in-line package; 42 leads (600 mil) sot270-1 1999 may 10 48 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 2.90 2.65 0.25 0.50 0.35 0.25 0.14 14.1 13.9 1 18.2 17.6 1.2 0.8 7 0 o o 0.2 0.1 0.2 1.95 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 sot319-2 95-02-04 97-08-01 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 1.2 0.8 d e q e a 1 a l p detail x l (a ) 3 b 19 y c e h a 2 d z d a z e e v m a 1 64 52 51 33 32 20 x pin 1 index b p d h b p v m b w m w m 0 5 10 mm scale qfp64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm sot319-2 a max. 3.20 1999 may 10 49 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 soldering introduction this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. through-hole mount packages s oldering by dipping or by solder wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joints for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg(max) ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. m anual soldering apply the soldering iron (24 v or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. surface mount packages r eflow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. w ave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. m anual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 1999 may 10 50 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 suitability of ic packages for wave, re?ow and dipping soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. for sdip packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. 3. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is only suitable for lqfp, qfp and tqfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. mounting package soldering method wave reflow (1) dipping through-hole mount dbs, dip, hdip, sdip, sil suitable (2) - suitable surface mount bga, sqfp not suitable suitable - hlqfp, hsqfp, hsop, htssop, sms not suitable (3) suitable - plcc (4) , so, soj suitable suitable - lqfp, qfp, tqfp not recommended (4)(5) suitable - ssop, tssop, vso not recommended (6) suitable - 1999 may 10 51 philips semiconductors preliminary speci?cation universal serial bus (usb) codec UDA1325 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011. ? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 1999 64 philips semiconductors C a worldwide company netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2886, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 62 5344, fax.+381 11 63 5777 for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 02 67 52 2531, fax. +39 02 67 52 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy printed in the netherlands 545002/750/01/pp52 date of release: 1999 may 10 document order number: 9397 750 02805 |
Price & Availability of UDA1325
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |